Peter Flake

Peter Flake

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Electronic Technology

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Peter Flake is Chief Scientific Officer of Imperas, Inc. Prior to joining Imperas, he was a Scientist of Synopsys, Inc. He was Chief Technology Officer of the Superlog language (SystemVerilog).
Mr. Flake was an Architect of Cadence Design Systems, Inc. Previously, he worked at Brunel University, and GenRad, Inc. Mr. Flake received a Master's degree from Cambridge University.

Former positions of Peter Flake

CompaniesPositionEnd
Corporate Officer/Principal -
CADENCE DESIGN SYSTEMS, INC. Corporate Officer/Principal -
Corporate Officer/Principal -
SYNOPSYS, INC. Corporate Officer/Principal -
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Technology Services

Electronic Technology

Technology Services

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Consumer Services