Synopsys, Inc. announced that TSMC has certified Synopsys' digital and custom design platforms for TSMC's 3-nanometer process technology. This certification, based on TSMC's latest design rule manual and process design kits (PDKs), is the result of an extensive collaboration with rigorous validation to deliver design solutions for optimized power, performance, and area, which accelerate the path to next-generation designs. Through a close collaboration with TSMC, Synopsys developed key enablement features and new technologies to ensure full-flow correlation from synthesis to place-and-route to timing and physical signoff for TSMC's N3 processes. Synopsys' Fusion Compiler™ RTL-to-GDSII solution and IC Compiler™ II place-and-route solution have been enabled with extended support of TSMC's N3 process. Synopsys' Design Compiler® NXT synthesis solution has been enhanced to enable designers to take full advantage of TSMC's 3nm technology, delivering improved quality of results and tighter correlation to Synopsys' IC Compiler™ II place-and-route solution using a new, highly accurate approach to resistance and capacitance estimation. The PrimeTime® signoff solution supports the advanced multi-input switching for accurate timing analysis and signoff closure. Additionally, Design Compiler NXT is enabled for TSMC N3 process for both HPC and mobile designs. To optimize some of the special features with the TSMC 3nm process technology, the Synopsys digital design platform has been enhanced to support pin density aware placement and global route modeling for better routing convergence on standard cell pins, concurrent legalization and optimization for faster timing convergence, a new cell map infrastructure to maximize available white space to improve PPA, interconnect optimization by auto generating via pillar structures and partial parallel routing for HPC design, and power-aware mixed driving strength multi-bit flip flop optimization for low-power designs. In the Synopsys custom design platform, Custom Compiler has been enhanced to accelerate the implementation of 3nm analog designs. These enhancements – co-developed with and validated by early 3nm users, including the Synopsys DesignWare® IP team – reduce the effort to meet new design rules and other 3nm technology requirements. The Synopsys HSPICE®, FineSim® and CustomSim™ simulation solutions deliver enhanced turnaround time for TSMC 3nm designs and provide signoff coverage for TSMC 3nm circuit simulation and reliability requirements.