Primarius Technologies will showcase its Design-Technology Co-Optimization (DTCO)-enabled EDA solutions powered by the latest generation SPICE and FastSPICE technologies at the Design Automation Conference (DAC) July 10-12 at Moscone Center in San Francisco. Demonstrations will highlight the more than 2X performance boost in SPICE and FastSPICE simulation with the introduction of NanoSpice X⢠and NanoSpice Pro X⢠that combines 10 plus years of continuous innovations on circuit simulation by Primariusâ team. NanoSpice X shows significant new improvements in large post-layout SPICE simulation for full-chip analog designs with complicated digital circuits where huge power and ground nets slowed SPICE simulation previously.
NanoSpice Pro X for FastSPICE simulation provides better performance and usability for challenging designs including advanced SRAM, DRAM, Flash and other large block or full-chip designs. Both circuit analysis solutions offer comprehensive high-yield and signal integrity analysis, aging and EM/IR simulation and advanced circuit checking capabilities. Primariusâ NanoCellâ¢, a next-generation cloud-ready standard cell library characterization solution, can provide accurate and near-linear scaling performance on more than 10,000 cores through industry-proven modeling and simulation engines.
The DAC demonstration will offer examples of its faster library characterization abilities for advanced process nodes. Other demonstrations will feature 9812ACâ¢, the first AC low-frequency dynamic noise test system for advanced process development, and SDEPâ¢, a spec-driven modeling automation platform for efficient and quality SPICE model auto-generation. Also, PCellLab⢠and PQLabâ¢, an intuitive, efficient and quality PCell auto-generation for PDK development platform with full PDK quality assurance capabilities.