Cadence Design Systems, Inc. expanded its system IP portfolio with the addition of the Cadence Janus Network-on-Chip (NoC). As larger, more complex SoCs and disaggregated multi-chip systems proliferate to accommodate escalating compute demands, data delivery within and between silicon components has become increasingly challenging--impacting power, performance and area (PPA). The Cadence Janus NoC manages these simultaneous high-speed communications efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.

The Cadence Janus noC leverages Cadence's legacy of trusted and time-proven Tensilica RTL generation tools. Customers can utilize Cadence's extensive portfolio of software and hardware for simulation and emulation of their NoC and gain deep insights into its performance using Cadence's System Performance Analysis tool (SPA). By enabling architectural exploration, this flow results in the best NoC design to meet product needs.

The NoC leverages Cadence's well-established leadership in IP and quality, backed by customer satisfaction for technical support. The Cadence Janus No C mitigates the routing congestion and timing issues associated with today's complex SoC interconnects, which often don't become apparent until physical implementation. Addressing the most pressing needs, Cadence's first-generation NoC provides a platform for future innovations, such as support for industry-standard memory and I/O coherence protocols.

Accelerated time to market: PPA-optimized RTL enables SoC designers to achieve their bandwidth and latency goals. Packized messages enable higher utilization of wires, reducing wire count and timing closure challenges. Lower risk: The NoC's built-in power management, clock domain crossing and width matching reduce design complexity.

Quick turnaround: Cadence's extensive simulation and emulation capabilities enable early architectural exploration, allowing quick validation of PPA results to ensure the configuration meets design requirements. Scalable architecture: Customers can design a subsystem and reuse it in a full SoC context of the NoC, allowing future reuse in a multi-chip system. Flexible: The NoC is compatible with any IP with an industry-standard interface, including AXI4 and AHB.