Avago Technologies Limited announced that its 25-Gbps Serializer/Deserializer (SerDes) core in 28-nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR). Achieving CEI-25G-LR compliance eases design of data networking applications and aligns with the push for 100G Ethernet Infrastructure to extend cloud computing, multimedia and virtualization capabilities. The company will demonstrate its 25G SerDes cores in backplane applications at the DesignCon 2012 exhibition in the Santa Clara Convention Center in Santa Clara, California from January 31 to February 1. The embedded SerDes cores are often integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The demonstrations, which show the Avago 25G SerDes running on over 30-inch PC board traces, will take place in the TE Connectivity booth (#411) and in the Amphenol TCS booth (#501). Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture, and Avago has integrated over 400 SerDes channels on a single ASIC. The 28-nm Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, data latency, and jitter and crosstalk tolerance.