Cadence Design Systems Inc. announced that Renesas Electronics Corporation shortened its design and verification time by 70% by utilizing Cadence(R) C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled the company to quickly offer their customers IP supporting this next-generation video codec. Renesas established its own coding style and reduced code size by almost half with SystemC to create the HEVC IP at a high level of abstraction.

This enabled verification times that were six times faster than register-transfer level (RTL). This approach also enabled Renesas to use C-to-Silicon Compiler to explore many algorithmic implementations to generate high-performance RTL while minimizing power consumption and chip area. To eliminate any potential schedule impact from a significant engineering change order (ECO) late in the project, Renesas developed an ECO flow utilizing C-to-Silicon Compiler with Encounter(R) Conformal(R) ECO Designer.

This allowed them to use high-level synthesis to quickly apply and verify a patch to stay on schedule.