Cadence Design Systems Inc. announced that Avago Technologies(R) used Cadence(R) Encounter(R) Digital Implementation (EDI) System to accelerate the design schedule and boost engineering productivity on a large-scale 28-nanometer networking chip. Avago achieved performance of 1GHz, a 57% improvement compared to the previous software. In addition, full-chip implementation turnaround time improved through faster timing closure and fewer design iterations.

Cadence is currently collaborating with Avago on its next high-speed networking chip-a 150 million-gate design. The EDI System provides an effective methodology to optimize power, performance, and area for high-performance, giga-scale designs. In addition, integrated "in-design" signoff capabilities in EDI System ensure correlation between timing and power calculations used during implementation and the final calculations produced by signoff engines, reducing iterations between the implementation and signoff stages, resulting in improved productivity for the design team.